The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), which may be realized as metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A MOS transistor may be realized as a p-type device (i.e., a PMOS transistor) or an n-type device (i.e., an NMOS transistor). Moreover, a semiconductor device can include both PMOS and NMOS transistors, and such a device is commonly referred to as a complementary MOS or CMOS device. A MOS transistor includes a gate electrode as a control electrode that is formed over a semiconductor substrate, and spaced-apart source and drain regions formed within the semiconductor substrate and between which a current can flow. The source and drain regions are typically accessed via respective conductive contacts formed on the source and drain regions. Bias voltages applied to the gate electrode, the source contact, and the drain contact control the flow of current through a channel in the semiconductor substrate between the source and drain regions beneath the gate electrode. Conductive metal interconnects (plugs) formed in an insulating layer are typically used to deliver bias voltages to the gate, source, and drain contacts.
The desire for higher chip density has driven the development of fabrication processes capable of producing devices with smaller dimensions. As devices become smaller, the pitch between the gate stacks of neighboring transistors (e.g., for a CMOS implementation) also becomes smaller. In turn, the available area for silicide contact regions between neighboring gate stacks shrinks in a proportional manner. This available area may also be referred to as the silicide contact window or the silicide window. As the silicide contact window shrinks, the corresponding contact resistance increases due to the reduction in the silicide-to-silicon junction area. High contact resistance is undesirable, and it can be very problematic for modern process node technologies, e.g., 65 nm, 45 nm, 32 nm, and other small scale technologies.
The silicide contact window for 90 nm technology is about 180 nm, the silicide contact window for 65 nm technology is about 140 nm, the silicide contact window for 45 nm technology is about 90 nm, and the silicide contact window for 32 nm technology is only about 60 nm. When progressing from 90 nm technology to 32 nm technology, the size of the spacers (which are formed on the sidewalls of the gate stacks) can be reduced somewhat in an effort to maintain a tolerable silicide contact window. However, the minimum spacer size can be limited when using smaller scale technologies such as 32 nm technology. In such situations, the size of the silicide contact window cannot be preserved, which results in an undesirably high contact resistance. For example, the external resistance (which is influenced by the contact resistance) for a typical NMOS transistor fabricated using 90 nm technology can be relatively low (about 270 ohm-μm), while the external resistance for a typical NMOS transistor fabricated using 32 nm technology can be relatively high (about 430 ohm-μm). The higher external resistance can significantly degrade device performance.